The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades

The GigaBit Transceiver (GBT) is a high-speed optical transmission system currently under development for HEP applications. This system will implement bi-directional optical links to be used in the radiation environment of the Super LHC. The GigaBit Transimpedance Amplifier (GBTIA) is the front-end optical receiver of the GBT chip set. This paper presents the GBTIA, a 5 Gbit/s, fully differential, and highly sensitive optical receiver designed and implemented in a commercial 0.13 μm CMOS process. When connected to a PIN-diode, the GBTIA displays a sensitivity better than −19 dBm for a BER of 10−12. The differential output across an external 50 Ω load remains constant at 400 mVpp even for signals near the sensitivity limit. The chip achieves an overall transimpedance gain of 20 kΩ with a measured bandwidth of 4 GHz. The total power consumption of the chip is less than 120 mW and the chip die size is 0.75 mm x 1.25 mm. Irradiation testing of the chip shows no performance degradation after a dose rate of 200 Mrad

The Level-0 Muon Trigger for the LHCb Experiment

A very compact architecture has been developed for the first level Muon Trigger of the LHCb experiment that processes 40 millions of proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 microseconds latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.Comment: 33 pages, 16 figures, submitted to NIM

Low power discriminator for ATLAS pixel chip

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers

XPAD: pixel detector for material sciences

Currently available 2D detectors do not make full use of the high flux and high brilliance of third generation synchrotron sources. The XPAD prototype, using active pixels, has been developed to fulfil the needs of materials science scattering experiments. At the time, its prototype is build of eight modules of eight chips. The threshold calibration of /spl ap/4 10/sup 4/ pixels is discussed. Applications to powder diffraction or SAXS experiments prove that it allows to record high quality data

CURVACE - CURVed Artificial Compound Eyes

International audienceCURVACE aims at designing, developing, and assessing CURVed Artificial Compound Eyes, a radically novel family of vision systems. This innovative approach will provide more efficient visual abilities for embedded applications that require motion analysis in low-power and small packages. Compared to conventional cameras, artificial compound eyes will offer a much larger field of view with negligible distortion and exceptionally high temporal resolution in smaller size and weight that will fit the requirements of a wide range of applications

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS

XPAD: A Photons Counting Pixel Detector for Material Sciences and Small Animal imaging

A paraître dans NIMInternational audienceExperiments on high flux and high brilliance 3rd generation synchrotron X-ray sources are now limited by detector performance. Photon counting hybrid pixel detectors are being investigated as a solution to improve the dynamic range and the readout speed of the available 2D detectors. The XPAD2 is a large surface hybrid pixel detector (68 x 65 mm$^2$) with a dynamic response which ranges from 0.01 photons/pixel/s up to 10$^6$ photons/pixel/s. High resolution data have been recorded using the XPAD2. The comparison with data measured using a conventional setup shows a gain on measurement duration by a factor 20 and on dynamic range. A new generation of pixel detector (XPAD3) is presently under development. For this, a new electronic chip (the XPAD3) has been designed to improve spatial resolution by using 130 $\mu$m pixels and detector efficiency by using CdTe sensors. XPAD2 is also operated with PIXSCAN, a CT-scanner for mice

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment